1. Technical Field
The present disclosure relates to a process for manufacturing an insulated-gate semiconductor power device and, more specifically, to a method for manufacturing a power MOS device of the type using a trench for insulating the gate of the device (hereinafter referred to as trench-gate device), as well as to a method for manufacturing a power MOS device or a device of the Insulated Gate Bipolar Transistor—IGBT-type.
2. Description of the Related Art
As is known, power MOS devices utilize a plurality of cells, each having its own gate adjacent to body and source regions. In the manufacturing process of trench-gate power MOS devices, in each elementary cell of the device, the gate of the MOS structure is made by digging a trench in the silicon substrate, coating the walls of the trench with a thin oxide layer, referred to as gate oxide, and then totally filling the trench with polysilicon. In this structure, the channel of the device is formed along the vertical walls of the trench.
A MOS structure formed by stacking of silicon, oxide, and polycrystalline silicon has considerable advantages as compared to a device made using planar technology. In fact, the resistance associated with the JFET area, due to the opposed body wells of the device, is totally eliminated, thus improving the performance characteristics of the device when it is on, and the dimensions of the device are scaled, thereby increasing the amount of current that can be carried relative to prior devices.
On the other hand, this structure has some problems. In fact, in the bottom area of the trench a crowding of the electric field lines is created, which brings about, for a same flowing current, a reduction in the breakdown voltage of the device. In addition, as compared to a planar structure, for a same active area, there occurs a considerable increase in the gate-oxide area, even in non-useful areas, where the channel is not formed, i.e., in the parts of the gate oxide that extend underneath the body. The increase in the area occupied by the gate oxide entails an increase in the parasitic capacitances linked to the gate terminal of the device, and hence in the gate charge as compared to planar structures.
The first problem (crowding of the field lines) is currently solved by providing the trench with a U-shaped profile, rounded at its bottom end. In this way, in fact, there is a smaller reduction in the breakdown voltage of the device. The second problem (increase in the gate oxide area), instead, is solved either by depositing in the trench a thick oxide layer, which coats only the bottom of the trench, following its U-shaped profile and thus forming a double gate-oxide layer in the bottom part of the trench, or else by depositing in the trench a thick oxide layer, which coats the bottom of the trench filling it up to a certain height.
The advantages deriving from the use of the above two process solutions are various:
an increase in the breakdown voltage of the device since the thick oxide layer performs the function of “field loop”, i.e., preventing crowding of the lines of electric field at the bottom of the trench;
an increase in the breakdown voltage of the gate oxide since the gate thin oxide no longer comprises the part of the wall where there is a variation in the crystallographic orientation of the silicon; in this area, in fact, the thickness of gate oxide is not controllable and could cause premature breakdown of the device;
a decrease in the parasitic capacitance linked to the gate terminal of the device; and
an achievement of a good compromise between the increase in the breakdown voltage and the reduction in the output resistance of the device.
A method used for depositing a thick oxide layer in the trench, which coats only the bottom of the trench following its U-shaped profile, is described in U.S. Pat. No. 6,528,355 B2. This patent discloses a method for obtaining a power MOS transistor with a trench as shown in the cross-sections of FIGS. 13a and 13b, which illustrate the structure half-way through the process and at the end of the process, respectively. The sequence of the fabrication steps is described hereinafter. An epitaxial layer 32 is grown on a silicon substrate 31 and material that functions as a mask (for example, a silicon dioxide layer) is deposited on the epitaxial layer 32. The epitaxial layer 32 is etched to form one or more trenches, using a photolithography for defining the mask. After mask removal, the walls and the bottom of the trenches are coated with a dielectric film (for example, silicon dioxide), which functions as a field oxide 41. The trench is then filled with an auxiliary layer (for example, photoresist), which is then etched so as to leave a plug 42 within the trench, the top surface whereof lies underneath the top surface of the semiconductor body.
Next, the field oxide 41 is wet etched chemically and partially removed so as to remain only on the bottom of the trench, following its U-shaped profile, where the field oxide is protected by the plug 42. The structure of FIG. 13a is thus obtained. Then, the plug 42 is removed and a gate insulating film 43 (for example, of silicon dioxide), thinner than the field oxide 41, is grown. Finally, a body 37, a gate 44 (of polycrystalline silicon that fills the trench), a source 38 and the corresponding metallizations are made, to obtain the structure of FIG. 13b (wherein, however, the metallizations are not shown, for sake of clarity).
The process just described has, however, many problems.
First, the process of etching the auxiliary layer intended to form the plugs 42 within the trenches is not readily controllable and can determine an erroneous sizing of the plugs, thus causing poor operation of the device. In particular, if the plugs 42 are not deep enough, i.e., they have a depth such that the thick oxide 41 reaches the channel area, the threshold voltage of the device becomes very variable. In addition, the variability of the depth of the plugs 42 brings about a variable surface ratio between the gate thin oxide and the thick oxide and consequently also causes variability in the capacitance between the gate terminal and the drain terminal. Finally, the variability in the depth of the plugs, and hence the variability in the passage between the gate thin oxide 43 and the thick oxide 41, alters the distribution of the lines of electric field with consequent alteration of the breakdown voltage of the device.
Another fundamental problem of the process described by the patent referred to above is that the wet etching of the thick oxide layer not covered by the plug 42 introduces critical conditions in controlling the distance D between the lower end of the body 37 and the top surface of the thick oxide 41 that coats the wall of the trench.
In fact, it is not easy during the deposition of the first auxiliary layer (photoresist) to fill the trench completely without forming voids and to maintain a constant distance D at every point of each single silicon wafer and, even more, to maintain it constant between two different silicon wafers.
This problem is particularly experienced when the etching of the auxiliary layer is made using an oxygen plasma, which, by its very nature, renders the etching isotropic, but is characterized by a non-uniformity in the etching rate (a non-uniformity of approximately 10-15%) between the different points of the silicon wafer and between two distinct silicon wafers.
Also the removal of the thick oxide from the wall of the trench not covered by the plug presents problems due to the fact that usually hydrofluoric-acid (HF) based solutions are used for the etching. In this case, the etching rate depends upon the concentration of the solution and upon the process temperature and is not uniform by approximately 5-10% in the different points of the silicon wafer and between two distinct silicon wafers. In addition, in wet etching it is possible to control only the etching time, but it is not possible to control the end point of the etching.
Finally, in current MOS structures, the attempt is made to provide trenches that are as narrow as possible (even smaller than 0.6 μm) so that capillarity phenomena could be triggered. This could cause, using the wet etching of the known process described above, significant variations in the etching rate and non-uniformity of the etching of the oxide inside the trench.
Consequently, it is particularly important to identify new strategies to overcome the problems of the prior methods and ensure that the etching for forming the trench has a rate that is as uniform as possible and that is such as to enable control of the end point of the etch.